1. Technical Field
This invention relates generally to memory devices, and more particularly, to a memory array which includes a plurality of resistive memory devices.
2. Background Art
FIG. 1 is a schematic representation of a portion of a DRAM memory array 100 proposed for 1-mega-bit class density. The array 100 includes a plurality of word lines (two shown at WL0, WL1), and a plurality of bit lines (one shown at BL0). The array includes a large number of similar memory cells (two memory cells MC0, MC1 shown in FIG. 1). The memory cell MC0 includes a capacitor C0 having one plate C0P1 connected to bit line BL0 and the other plate C0P2 connected to the drain D0 of an MOS transistor T0. The word line WL0 is connected to the gate G0 of the transistor T0. Likewise, the memory cell MC1 includes a capacitor C1 having one plate C1P1 connected to bit line BL0 and the other plate C1P2 connected to the drain D1 of an MOS transistor T1. The sources S0, S1 of these transistors T0, T1 are connected together, resulting in what is called a common-source (CS) memory array 100. It will be understood that the two cells MC0, MC1 shown and described are part of a large number of such memory cells in the array 100.
The data storing mechanism of each memory cell is based upon the presence or absence of electric charge accumulated in the capacitor. The presence or absence of the electric charge in the capacitor can be sensed by means of sense amplifier SA (connected to a bit line BL0), sensing current in the bit line BL0.
FIG. 2 is a cross-sectional view of an implementation of the structure of FIG. 1. As shown, the structure of FIG. 2 includes a p type silicon semiconductor substrate SS having spaced n+ diffused regions n+1, n+1, n+3 therein. The region n+1 and the region n+2 make up the drain and source of transistor T0 which includes gate oxide and gate WL0 (G0), while the region n+3 and the region n+2 make up the drain and source of transistor T1 which includes gate oxide and gate WL1 (G1). Polycrystalline silicon layers C0P2, C1P2 are provided in contact with the respective drain regions n+1, n+3 of the transistors T0, T1, and a dielectric film I is provided as shown, separating the layers C0P2, C1P2 from the gates WL0, WL1 of the transistors T0, T1. A layer of metal BL0 is formed over the dielectric film I. The metal layer BL0 is separated from the polycrystalline silicon layers C0P2, C1P2 by the dielectric film I, so that metal layer BL0 and layer C0P2 form capacitor G0, while metal layer BL0 and layer C1P2 form capacitor C1. The central n+ region n+2, commonly used by the transistors T0, T1, acts as the common source of the transistors T0, T1.
FIG. 3 is a graph illustrating typical drain-to-source (IDS) current flow through a transistor of the array as described above, for increasing drain-to-source voltage (VDS), based on increasing steps in the gate-to-source voltage (VGS) of the transistor. If VDS and VGS are kept relatively low (for example with VGS limited to 2 V, and VDS limited to 3 V, current through the transistor is limited to 30 ua).
FIG. 4 illustrates a two-terminal metal-insulator-metal (MIM) resistive memory device 130. The memory device 130 includes a metal, for example copper electrode 132, an active layer 134 of for example copper oxide on and in contact with the electrode 132, and a metal, for example copper electrode 136 on and in contact with the active layer 134. With reference to FIG. 5, initially, assuming that the memory device 130 is unprogrammed, in order to program the memory device 130, ground is applied to the electrode 132, while a positive voltage is applied to electrode 136, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory device 130 from a higher to a lower electrical potential in the direction from electrode 136 to electrode 132. Upon removal of such potential the memory device 130 remains in a conductive or low-resistance state having an on-state resistance.
In the read step of the memory device 130 in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory device 130 from a higher to a lower electrical potential in the direction from electrode 136 to electrode 132. This electrical potential is less than the electrical potential Vpg applied across the memory device 130 for programming (see above). In this situation, the memory device 130 will readily conduct current, which indicates that the memory device 130 is in its programmed state.
In order to erase the memory device 130, a positive voltage is applied to the electrode 132, while the electrode 136 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory device 130 from a higher to a lower electrical potential in the direction of from electrode 132 to electrode 136.
In the read step of the memory device 130 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 130 from a higher to a lower electrical potential in the direction from electrode 136 to electrode 132 as described above. With the active layer 134 (and memory device 130) in a high-resistance or substantially non-conductive state, the memory device 130 will not conduct significant current, which indicates that the memory device 130 is in its erased state.
FIG. 6 is a schematic representation of a portion of a typical resistive memory device array 200. The array 200 includes a plurality of word lines (two shown at WL0, WL1), and a plurality of bit lines (one shown at BL0). The array 200 includes a large number of similar memory cells (two memory cells M0, M1 shown in FIG. 6). The memory cell M0 includes a resistive memory device RM0 as described above and as illustrated in FIG. 4, having one electrode RM0E1 connected to bit line BL0 and the other electrode RM0E2 connected to the drain D0 of an MOS transistor T0. The word line WL0 is connected to the gate G0 of the transistor T0. Likewise, the memory cell M1 includes a resistive memory device RM1 having one electrode RM1E1 connected to bit line BL0 and the other electrode RM1E2 connected to the drain D1 of an MOS transistor T1. The sources S0, S1 of these transistors T0, T1 are connected together, resulting in a common-source (CS) memory array. It will be understood that the two cells M1, M2 shown and described are part of a large number of such memory cells in the array 200. A sense amplifier SA is connected to bit line.
It will be seen that the structure of FIG. 6 is similar to that of FIG. 1, but with the capacitors replaced by resistive memory devices.
FIG. 7 illustrates a larger portion of the array 200 of FIG. 6, with the common source CS connected to ground. Typically, the programming and erasing of a resistive memory device of the array 200 requires a substantially larger current therethrough than the current described above for a DRAM cell. In addition, and with reference to FIG. 7, with a large number of bit lines connected to each word line (for example bit lines BL0-BL7 connected to a word line WL0, or in actual implementation more than 256 bit lines connected to the same section driving line to minimize array area), it will be seen that upon selection of a word line, for example word line WL0, all current in the bit lines BL0-BL7 will flow through the common source CS to ground. These conditions result in the common source CS carrying high levels of current. In such situation, it is highly desirable to provide a low common source resistance, to reduce voltage drop therein, so as to keep the operating speed at an appropriate level, and to also provide high transistor drivability attributable to the grounded source bias condition to insure high performance of the array.
Therefore, what is needed is a resistive memory device array which includes a low-resistance common source and high drivability characteristics.